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PSL IP Source Files for POWER9 CAPI

These POWER9 service layer (PSL9) IP source files are provided by IBM for use with the open source CAPI2.0 board support repository https://github.com/open-power/capi2-bsp to create the necessary card specific infrastructure for the Coherent Accelerator Processor Interface version 2.0 (CAPI 2.0). Important Note: These are Advance documents. The...


Vital Product Data Records for OpenPOWER Field Replaceable Units User's Guide

This document explains how to create vital product data (VPD) records for OpenPOWER field replaceable unit (FRU) cards. The FRU VPD contains information describing the card assembly. It contains the part number and serial number of the FRU, the manufacturer of the FRU, and much more. In some instances, the FRU VPD contains data that is used to initialize...


POWER9 Thermal and Mechanical Reference Guide for the Sforza SCM

This reference guide provides the mechanical and packaging specification for the IBM® POWER9™ processor. It describes the thermal modeling of the POWER9 processor and the memory subsystem.


POWER8 Processor for the Single-Chip Module Datasheet

This datasheet is a technical reference for the IBM® POWER8® processor for the single-chip module (SCM), which consists of a single POWER8 processor. Each processor can have up to 12 cores enabled. The 12-core POWER8 processor is designed for use in servers and large-cluster systems. It uses CMOS 22 nm SOI technology with 15 metal layers....


POWER9 Sforza Platform Design Guide

The IBM® POWER9™ processor is a superscalar symmetric multiprocessor designed for use in servers and large-cluster systems. It supports direct-attach memory and a maximum symmetric multiprocessing (SMP) size of two sockets. It is targeted for scale-out workloads. Topics covered in the design guide include: The power delivery system ...


POWER9 LaGrange Single-Chip Module Datasheet

This datasheet describes the IBM® POWER9™ processor. The POWER9 processor is a superscalar symmetric multiprocessor designed for use in servers and large-cluster systems. It uses 14 nm technology with 17 metal layers. The POWER9 processor can have up to 24 cores enabled on a single chip. It supports direct-attach memory and a maximum...


POWER8 Memory Buffer DDR4 Application User's Guide

This document describes the requirements and wiring rules for the IBM POWER8 memory buffer DDR4 application. The POWER8 memory buffer is a synchronous memory interface chip, manufactured using the 22 nm CMOS 14S technology. It has four memory ports and 16 MB of cache. A high-speed differential memory interface (DMI) connects the memory buffer to...


POWER9 LaGrange Platform Design Guide

The IBM® POWER9™ processor is a superscalar symmetric multiprocessor designed for use in servers and large-cluster systems. It supports direct-attach memory and a maximum symmetric multiprocessing (SMP) size of two sockets. It is targeted for scale-out workloads. Topics covered in the design guide include: The power delivery system ...


POWER9 eATX Reference Design for the Sforza SCM

The specialized schematic and layout files described in this document support the IBM® POWER9™ eATX reference design for the Sforza single-chip module (SCM). Used with EDA software from Cadence Design Systems, Inc., these files enable the efficient design of PCBs for the POWER9 eATX reference design.


POWER9 Memory Subsystem for DDR4 IS RDIMMs Validation Guide

This document covers the following aspects of the OpenPOWER memory subsystem: Power-on Bring-up Characterization Reliability, Availability and Serviceability (RAS) Power, Thermal, and Performance Dual in-line memory module (DIMM) Supplier Qualification for the OpenPOWER platform

IBM Portal for OpenPOWER Open Forum in Slack (non-confidential)

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