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    • POWER8

      Based on IBM® Power Architecture®, IBM® POWER8® systems are optimized for the cloud, big data, and analytics. They consist of superscalar multiprocessors that are massively multithreaded. POWER8 systems incorporate the high-speed differential POWER8 memory buffer, which supports several DDR technologies. POWER8 systems use the Coherent Accelerator Processor Interface (CAPI) to attach specialized processors, and permit them direct access to the memory address space.

        • POWER8 System Design

          System designers can use this material to develop systems that make effective use of of IBM® POWER8® components, modules, and interfaces. The information provided relates to power and thermal requirements, hardware validation, design rules, and the memory subsystem.

            • System Test (POWER8)

              These documents describe the recommendations for testing and verifying an IBM® POWER8® system.

            • System Firmware (POWER8)

              These links and documentation provide details related to the System Firmware in support of designing an IBM® POWER8® system.

              Introduction to Power, Thermal, and the On-Chip Controller (OCC)

              This presentation introduces the on-chip controller (OCC). The OCC provides access to detailed temperature, power, and utilization data. It also enables control of processor frequency, voltage, and memory bandwidth. This enables customization of performance and energy management.

              Read More & Download | Provide Feedback |  | Revision Date: 03/21/2016

              OpenPOWER Firmware Documentation

              This link takes you to the OpenPOWER Firmware Documentation Repository on GitHub. The repository contains documentation for the OpenPOWER open source firmware that's being released to support the POWER ecosystem.

              Read More & Download | Provide Feedback |  | Revision Date: 10/05/2015

              OpenPOWER Firmware Training Videos

              The OpenPOWER Firmware Training Videos are a series containing information about the Firmware IBM donated to the OpenPOWER Foundation. This series of videos should serve as a fast way to understand the concepts and get to real development faster. See read me file for details of material provided and sequence for use.

              Read More & Download | Provide Feedback |  | Revision Date: 06/16/2015

            • Reference Design Examples (POWER8)

              These reference designs describe the essential components of an IBM® POWER8® system. Third parties may copy, enhance, and modify these designs. Use of these designs enables engineers to quickly evaluate systems and may reduce product development time.

                • DDR4 Memory Riser Card (POWER8)

                  These documents describe the IBM® POWER8® memory riser cards with DDR4 SDRAM.

                  OpenPOWER POWER8 DDR4 Memory Riser Design Files

                  These specialized files support the IBM POWER8 memory buffer. Used with EDA software from Cadence Design Systems, Inc., they enable the efficient design of PCBs for the OpenPOWER POWER8 DDR4 memory riser design. Schematics are provided in both native format and as a PDF file. Layout, card outline, and cross section files, a bill of materials, and...

                  Read More & Download | Provide Feedback |  | Revision Date: 04/24/2017

                  POWER8 Memory Buffer Design Files

                  The attached files support the design of OpenPOWER products that use the IBM POWER8 Memory Buffer. The schematic pdf contains information on the value, size, and quantity of capacitors and calibration resistors that must be placed under (on the backside of) the POWER8 Memory Buffer module. The two Allegro board files show correct placement of these...

                  Read More & Download | Provide Feedback |  | Revision Date: 04/17/2015

                • DDR3 Memory Riser Card (POWER8)

                  These documents describe the IBM® POWER8® memory riser cards with DDR3 SDRAM.

                  OpenPOWER POWER8 DDR3 Memory Riser Design Files

                  These specialized files, when used with electronic design automation (EDA) software from Cadence Design Systems, Inc., enable the efficient design of printed circuit boards (PCBs) for an OpenPOWER POWER8 DDR3 Memory Riser. Schematics are provided in both native format and as a PDF file. A layout file, a bill of material, cross section, card outline,...

                  Read More & Download | Provide Feedback |  | Revision Date: 08/24/2015

                  POWER8 Memory Buffer Design Files

                  The attached files support the design of OpenPOWER products that use the IBM POWER8 Memory Buffer. The schematic pdf contains information on the value, size, and quantity of capacitors and calibration resistors that must be placed under (on the backside of) the POWER8 Memory Buffer module. The two Allegro board files show correct placement of these...

                  Read More & Download | Provide Feedback |  | Revision Date: 04/17/2015

                • 2-Socket Reference Design for POWER8 (Memory Riser Card Required)

                  This material supports 2-socket IBM® POWER8® designs.

            • Programmable Components (POWER8)

              Many components of an IBM® POWER8® system are programmable. These documents describe the required components and how to acquire them. Where appropriate, they also describe how to program the components.

              APSS Microcontroller Programming Guide

              This document describes how to program the analog power system sweep (APSS) microcontroller in IBM® POWER8® systems.

              Read More & Download | Provide Feedback |  | Revision Date: 09/29/2015

              SPIVID PSoC Device Programming Guide

              This document describes how to program the Cypress Programmable System-on-Chip (PSoC) with the serial peripheral interface voltage identification (SPIVID) information for IBM® POWER8® systems.

              Read More & Download | Provide Feedback |  | Revision Date: 09/29/2015

              SPIVID Programming Cable Build Instructions

              This document describes how to build the serial peripheral interface voltage identification (SPIVID) cable. An SPIVID cable is connected to the JTAG interface so that the Cypress CY8C3245LTI-163 programmable system-on-chip (PSoC) can be programmed with the VID code. The SPIVID cable is not available commercially; it must be built by the user.

              Read More & Download | Provide Feedback |  | Revision Date: 09/29/2015

              OpenPOWER POWER8 Programmable Components

              This document lists the programmable parts needed for an OpenPOWER IBM® POWER8® system. It explains what components are needed, how to procure the components , and where appropriate, the programming procedure for them. The compressed file named P8_Programmables is used in conjunction with this document.

              Read More & Download | Provide Feedback |  | Revision Date: 09/29/2015

              SPIVID Voltage Control Interface User's Manual

              This document describes the voltage control interface (VCI) used for serial peripheral interface (SPI) voltage identification (VID).

              Read More & Download | Provide Feedback |  | Revision Date: 09/29/2015

              APSS Programming Cable Build Instructions

              This document describes how to build the analog power system sweep (APSS) cable. An APSS cable connects the Texas Instruments XDS100v2 USB-to-JTAG emulator card dongle to the J8 connector on the target board that has the APSS part to be programmed. The APSS cable is not available commercially; it must be built by the user.

              Read More & Download | Provide Feedback |  | Revision Date: 09/28/2015

              APSS Programming Cable Bill of Materials

              This spreadsheet lists the material needed to build the APSS programming cable.

              Read More & Download | Provide Feedback |  | Revision Date: 09/25/2015

              SPIVID Programming Cable Bill of Materials

              This spreadsheet lists the material needed to build the SPIVID programming cable.

              Read More & Download | Provide Feedback |  | Revision Date: 09/25/2015

              Vital Product Data Records for OpenPOWER Field Replaceable Units User's Guide

              This document explains how to create vital product data (VPD) records for OpenPOWER field replaceable unit (FRU) cards. The FRU VPD contains information describing the card assembly. It contains the part number and serial number of the FRU, the manufacturer of the FRU, and much more. In some instances, the FRU VPD contains data that is used to initialize...

              Read More & Download | Provide Feedback |  | Revision Date: 09/03/2015

            • Mechanical and Thermal (POWER8)

              These documents describe mechanical and thermal features of an IBM® POWER8® system.

              POWER8 Thermal and Mechanical Reference Guide

              This reference guide provides the mechanical and packaging specification for the IBM® POWER8® processor. It describes the thermal modeling of the POWER8 processor, the POWER8 memory buffer, and the memory subsystem.

              Read More & Download | Provide Feedback |  | Revision Date: 10/15/2019

              POWER8 Processor Power Maps for the Single-Chip Module

              This spreadsheet presents power maps for the IBM POWER8 processor single-chip module.

              Read More & Download | Provide Feedback |  | Revision Date: 05/01/2015

            • Design Guidelines (POWER8)

              These documents describe the recommendations, rules, and requirements for designing an IBM® POWER8® system.

              POWER8 Single-Chip Module and POWER8 Memory Buffer Schematic Checklist

              The POWER8 SCM checklist is designed to support responses for up to a 2-socket system. The POWER8 memory buffer checklist is designed to support responses for up to eight memory buffers, which is a 2-socket system using all four DMI ports on each processor.

              Read More & Download | Provide Feedback |  | Revision Date: 09/11/2017

              OpenPOWER Memory Subsystem for DDR4 ISRDIMMs Validation Guide

              This document covers the following aspects of the OpenPOWER memory subsystem: Power-on Bring-up Characterization Reliability, availability, and serviceability (RAS) Power Basic performance Dual in-line memory module (DIMM) qualification for the OpenPOWER platform

              Read More & Download | Provide Feedback |  | Revision Date: 09/13/2016

              POWER8 Single-Chip Module (SCM) and POWER8 Memory Buffer Layout Checklist

              This checklist provides physical and layout checks for the POWER8 single chip module (SCM) and the POWER8 memory buffer. There are checks for clocks, the various buses, DDR3 and DDR4 memory, and power integrity. The POWER8 single-chip module (SCM) checklist is designed to support responses for a system with up to two sockets. The POWER8 memory buffer...

              Read More & Download | Provide Feedback |  | Revision Date: 07/26/2016

              POWER8 Memory Buffer DDR4 Application User's Guide

              This document describes the requirements and wiring rules for the IBM POWER8 memory buffer DDR4 application. The POWER8 memory buffer is a synchronous memory interface chip, manufactured using the 22 nm CMOS 14S technology. It has four memory ports and 16 MB of cache. A high-speed differential memory interface (DMI) connects the memory buffer to...

              Read More & Download | Provide Feedback |  | Revision Date: 07/24/2016

              Power Systems Host Bridge 3 (PHB3)

              The IBM Power Systems Host Bridge 3 (PHB3) is a core used on the Power Systems POWER8 microprocessor. The PHB3 provides a PCIe Gen 3 root complex port to connect to an adapter slot, a link to a PCIe switch, or a PCIe cable connection. The PHB3 is part of a larger unit called the PCI Express controller (PEC), which also contains a common queue (CQ)...

              Read More & Download | Provide Feedback |  | Revision Date: 05/31/2016

              POWER8 PCIe Controller Functional Specification

              This document describes the design and operation of the IBM POWER8 PCI Express Controller (PEC). It provides details on its basic requirements, function, operation, and usage. The PEC provides a PCIe Gen3 root complex port to connect to an adapter slot, or as a link to a PCIe switch. It acts as a PCIe host bridge from the internal, coherent processor...

              Read More & Download | Provide Feedback |  | Revision Date: 05/16/2016

              OpenPOWER DAS Functional Verification

              This document describes how to perform functional verification of direct attached storage (DAS) host bus adapter (HBAs) and redundant array of independent disks (RAID) adapters on an OpenPOWER platform.

              Read More & Download | Provide Feedback |  | Revision Date: 04/29/2016

              Petitboot Support for I/O Devices and Utilities

              Petitboot is a platform-independent boot loader that uses event mechanisms to dynamically update its knowledge of available configurations for system start. In OpenPOWER systems, Petitboot performs tasks such as installing operating systems, running utilities for SAN configuration, and running diagnostics. This document describes Petitboot support...

              Read More & Download | Provide Feedback |  | Revision Date: 04/26/2016

              IBM Methodology for Adding Signal-Integrity Guidelines for High-Speed Interconnections to the Cadence Allegro Constraint Manager

              This document describes the methodology used to add IBM signal integrity (SI) guidelines for OpenPOWER systems into the Cadence Allegro 16.5 Constraint Manager for the PCIe, A bus, and DMI.

              Read More & Download | Provide Feedback |  | Revision Date: 03/22/2016

              POWER8 Processor Bus Topology Design Guidelines

              This document describes the requirements and wiring rules for the IBM POWER8 processor bus topology. Topics covered include: Eye-Opening Requirements End-to-End Skew Timing Requirements Differential Memory Interface (DMI) Wiring Rules Symmetric Multiprocessing (SMP) A-Bus Wiring Rules PCIe Gen3 Bus Wiring Rules Phase-Locked Loop (PLL) Wiring Rules Reference...

              Read More & Download | Provide Feedback |  | Revision Date: 02/22/2016

              Network Interface Controllers Enablement and Functional Compliance Guidelines

              This document provides system integrators and I/O adapter vendors with information and test procedures to ensure the basic functionality of network interface controllers (NICs) and their compatibility with IBM Power Architecture. This document provides guidelines to verify hardware, firmware, and drivers on an OpenPOWER platform.

              Read More & Download | Provide Feedback |  | Revision Date: 10/23/2015

              POWER8 Memory Buffer DDR3 Application User's Guide

              This document describes the requirements and wiring rules for the IBM POWER8 Memory Buffer DDR3 application. The POWER8 Memory Buffer is a synchronous memory interface chip, manufactured using the 22 nm CMOS 14S technology. It has four memory ports and 16 MB of cache. A high-speed differential memory interface (DMI) connects the memory buffer to...

              Read More & Download | Provide Feedback |  | Revision Date: 09/30/2015

        • POWER8 Processor

          The IBM® POWER8® Processor is a superscalar symmetric multiprocessor designed for use in servers and large-cluster systems. Based on IBM® Power Architecture®, it provides even more performance than its predecessors while increasing the memory bandwidth and I/O speed. The chip uses a 22 nm silicon-on-insulator (SOI) fabrication process with 15 metal layers. The POWER8 processor provides significant performance at the thread, core, and system levels. It is optimized for efficiency, enables autonomic system optimization, and provides excellent big data analytics capability

          In the single-chip module (SCM) configuration, the processor can have up to 12 cores on a single chip. Each core has eight threads using simultaneous multithreading (SMT). The SMT is dynamically tunable, so that each core can have one, two, four, or eight threads.

          POWER8 Processor for the Single-Chip Module Datasheet

          This datasheet is a technical reference for the IBM® POWER8® processor for the single-chip module (SCM), which consists of a single POWER8 processor. Each processor can have up to 12 cores enabled. The 12-core POWER8 processor is designed for use in servers and large-cluster systems. It uses CMOS 22 nm SOI technology with 15 metal layers....

          Read More & Download | Provide Feedback |  | Revision Date: 08/08/2018

          POWER8 Processor SCM and Memory Buffer Hardware Errata Notice

          This document describes known errata applicable to the POWER8 Processor Single-Chip Module (SCM) or the POWER8 Memory Buffer along with the workarounds. An erratum is identified if the actual operation of one of these POWER8 devices differs from the functionality documented in the corresponding User’s Manual or Datasheet. Each erratum is assigned...

          Read More & Download | Provide Feedback |  | Revision Date: 08/30/2016

          Performance

          These white papers explore performance benefits of the processor.

          Read More & Download | Provide Feedback |  | Revision Date: 06/21/2016

          POWER8 Processor User's Manual for the Single-Chip Module

          The link below will take you to the POWER8 Processor User's Manual for the Single-Chip Module: POWER8 Processor User's Manual for the Single-Chip Module This user's manual describes the IBM POWER8 processor single-chip module (SCM): its features, facilities, components, and use. It provides information about the POWER8 processor from a programming...

          Read More & Download | Provide Feedback |  | Revision Date: 03/16/2016

          POWER8 Common Registers Specification

          This document describes the IBM® POWER8® registers used by both the POWER8 Processor and the POWER8 Memory Buffer. These registers are referred to as "common" registers. This manual is intended for system software and hardware developers and application programmers who want to develop products for the POWER8 processor or the POWER8 memory...

          Read More & Download | Provide Feedback |  | Revision Date: 07/30/2014

        • POWER8 Miscellaneous Material

          This material is POWER8 miscellaneous material.

          Additional POWER8 and CAPI Resources

          This document lists additional POWER8 and Coherent Accelerator Processor Interface (CAPI) resources of interest to the development community that are not located on the OpenPOWER Connect website.

          Read More & Download | Provide Feedback |  | Revision Date: 04/28/2016

          OpenPOWER POWER8 System Design Frequently Asked Questions

          This document answers the most commonly asked OpenPOWER and POWER8 questions. In addition to questions about POWER8 hardware and firmware questions, questions about the Coherent Accelerator Processor Interface (CAPI) and the POWER8 Functional Simulator are addressed.

          Read More & Download | Provide Feedback |  | Revision Date: 02/02/2016

        • POWER8 Memory Buffer

          The IBM® POWER8® Memory Buffer supports multiple system configurations. It uses a high-speed differential interface to communicate with a processor chip using a memory-agnostic protocol. This enables the memory buffer to support several DDR memory technologies without the need for a processor upgrade. The maintenance and calibration functions for the memory controller and associated memory inter­face are initiated and contained within the memory buffer chip. The Memory Buffer also contains a 16 MB on-board cache to support prefetching and to improve system performance.

          POWER8 Memory Buffer FC PBGA Marking Drawing

          This document identifies the markings on the flip-chip (FC) plastic ball grid array (PBGA) package for the POWER8 Memory Buffer.

          Read More & Download | Provide Feedback |  | Revision Date: 11/01/2016

          POWER8 Processor SCM and Memory Buffer Hardware Errata Notice

          This document describes known errata applicable to the POWER8 Processor Single-Chip Module (SCM) or the POWER8 Memory Buffer along with the workarounds. An erratum is identified if the actual operation of one of these POWER8 devices differs from the functionality documented in the corresponding User’s Manual or Datasheet. Each erratum is assigned...

          Read More & Download | Provide Feedback |  | Revision Date: 08/30/2016

          POWER8 Processor with NVIDIA NVLink Interconnect and POWER8 Memory Buffer Hardware Errata Notice

          This document describes known errata applicable to the IBM POWER8 processor with NVIDIA NVLink interconnect and the POWER8 memory buffer. It also describes any workarounds. An erratum is identified if the actual operation of one of these POWER8 devices differs from the functionality documented in the corresponding user’s manual or datasheet....

          Read More & Download | Provide Feedback |  | Revision Date: 08/30/2016

          POWER8 Memory Buffer DDR4 Application User's Guide

          This document describes the requirements and wiring rules for the IBM POWER8 memory buffer DDR4 application. The POWER8 memory buffer is a synchronous memory interface chip, manufactured using the 22 nm CMOS 14S technology. It has four memory ports and 16 MB of cache. A high-speed differential memory interface (DMI) connects the memory buffer to...

          Read More & Download | Provide Feedback |  | Revision Date: 07/24/2016

          POWER8 Memory Buffer Datasheet for DDR3 Applications

          This datasheet is a technical reference for the IBM POWER8 Memory Buffer. It contains detailed technical information including interface definitions, input/output (I/O) signals, electrical specifications, timing specifications, and other related information. The POWER8 Memory Buffer is a synchronous memory interface chip, manufactured using the 22...

          Read More & Download | Provide Feedback |  | Revision Date: 01/14/2016

          POWER8 Memory Buffer IBIS Models

          The Input/Output Buffer Information (IBIS) models for the IBM® POWER8® Memory Buffer provide information about the characteristics of the pins associated with this product. Developers can use this information to include the POWER8 Memory Buffer in their simulations.

          Read More & Download | Provide Feedback |  | Revision Date: 01/08/2016

          POWER8 Memory Buffer DDR3 Application User's Guide

          This document describes the requirements and wiring rules for the IBM POWER8 Memory Buffer DDR3 application. The POWER8 Memory Buffer is a synchronous memory interface chip, manufactured using the 22 nm CMOS 14S technology. It has four memory ports and 16 MB of cache. A high-speed differential memory interface (DMI) connects the memory buffer to...

          Read More & Download | Provide Feedback |  | Revision Date: 09/30/2015

          POWER8 Memory Buffer Registers Specification

          This document describes the IBM POWER8 registers used by the POWER8 memory buffer. The manual is intended for system software and hardware developers and application programmers who want to develop products for the POWER8 memory buffer.

          Read More & Download | Provide Feedback |  | Revision Date: 09/30/2015

          POWER8 Memory Buffer Datasheet for DDR4 Applications

          This datasheet is a technical reference for the IBM POWER8 Memory Buffer. It contains detailed technical information including interface definitions, input/output (I/O) signals, timing specifications, and other related information. The POWER8 Memory Buffer is a synchronous memory interface chip, manufactured using the 22 nm CMOS 14S technology with...

          Read More & Download | Provide Feedback |  | Revision Date: 07/10/2015

          POWER8 Memory Buffer Models: Physical Geometry and Thermal Characteristics

          These model files can be used to model the physical geometry and thermal characteristics of a cooling design for an IBM® POWER8® Memory Buffer Subsystem. One model was developed for use with the ANSYS Icepak computational fluid dynamics (CFD) software. The other models were developed for use with the Mentor Graphics FloTHERM CFD analysis...

          Read More & Download | Provide Feedback |  | Revision Date: 04/30/2015

          POWER8 Common Registers Specification

          This document describes the IBM® POWER8® registers used by both the POWER8 Processor and the POWER8 Memory Buffer. These registers are referred to as "common" registers. This manual is intended for system software and hardware developers and application programmers who want to develop products for the POWER8 processor or the POWER8 memory...

          Read More & Download | Provide Feedback |  | Revision Date: 07/30/2014

          POWER8 Memory Buffer User's Manual

          This user's manual describes the IBM® POWER8® memory buffer: its features, dual inline memory module (DIMM) configuration and addressing, the memory buffer cache, the DDR interface, and power and thermal management.

          Read More & Download | Provide Feedback |  | Revision Date: 04/22/2014

          POWER8 Memory Buffer Packaging Applications Guide FC PBGA

          This guide provides general second-level assembly process recommendations for an assembly manufacturer to use, based on IBM usage of the process to qualify a flip-chip plastic ball grid array (FC-PBGA) module. The technology described in this document addresses a module package that uses a C4 chip joined to an organic-based, multilayer, laminate...

          Read More & Download | Provide Feedback |  | Revision Date: 03/28/2014

          POWER8 Memory Buffer Physical Outline Drawing

          This document provides the physical outline of the flip-chip plastic ball grid array (FC PBGA) package for the POWER8 Memory Buffer.

          Read More & Download | Provide Feedback |  | Revision Date: 03/25/2014

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