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    • Coherent Accelerator Processor Interface (CAPI)

      The Coherent Accelerator Processor Interface (CAPI) eliminates the complexity and overhead of an I/O subsystem. It enables a custom accelerator to operate as part of the coherent fabric of a POWER8 chip or a POWER9 chip. CAPI provides a high-performance solution for the implementation of customer-specific, computation-heavy algorithms on a field-programmable gate array (FPGA).

      For more information about CAPI, see:

      Documents associated to the: Coherent Accelerator Processor Interface (CAPI) category

      PSL Checkpoint Files for the POWER8 CAPI SNAP Design Kit

      The CAPI storage, network, analytics programming (SNAP) enablement framework simplifies FPGA accelerator development. This framework enables application programmers to implement FPGA acceleration and CAPI technology. The power service layer (PSL) checkpoint files provided by IBM are for use with Xilinx Vivado software version 2017.4. They are intended...

      Read More & Download | Provide Feedback |  | Revision Date: 09/17/2018

      PSL IP Source Files for POWER9 CAPI

      These POWER9 service layer (PSL9) IP source files are provided by IBM for use with the open source CAPI2.0 board support repository https://github.com/open-power/capi2-bsp to create the necessary card specific infrastructure for the Coherent Accelerator Processor Interface version 2.0 (CAPI 2.0). Important Note: These are Advance documents. The...

      Read More & Download | Provide Feedback |  | Revision Date: 06/28/2018

      PSL Checkpoint Files for the Nallatech POWER8 CAPI Design Kit

      These power service layer (PSL) checkpoint files are provided by IBM for use with the Nallatech design kit for the Coherent Accelerator Processor Interface (CAPI). Important Note: These are Advance documents. The information is subject to change without notice. Contact your IBM representative before finalizing a design based on this documentation....

      Read More & Download | Provide Feedback |  | Revision Date: 03/31/2016

      PSL Checkpoint Files for the Alpha Data POWER8 CAPI Design Kit

      These power service layer (PSL) checkpoint files are provided by IBM for use with the Alpha Data design kit for the Coherent Accelerator Processor Interface (CAPI). Important Note: These are Advance documents. The information is subject to change without notice. Contact your IBM representative before finalizing a design based on this documentation....

      Read More & Download | Provide Feedback |  | Revision Date: 03/30/2016

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